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Using Fast Page Mode Dynamic Memories for Sampling

A speciel mode of the Fast Page Mode DRAM's was the CAS Before RAS Refresh Counter Test Cycle. It is a full-documented cycle, described in e.g. Siemens HYB 514256 (262144 x 4) datasheet.

The idea is to combine a CAS before RAS refresh cycle and a read / write cycle. The refresh counter is used as Row Address. When entering the CAS before RAS refresh cycle will the Row Address be loaded, and since the memory not remember if it begin on a standard R/W cycle, or a refresh cycle, will it be possible to continue by reading in page mode with default Row Address.

The HYB 514256 has 512 refresh cycles, and it is possible to use the refresh counter for loading the row address by using the CAS Before RAS Refresh Counter Test Cycle.

The mode was intended for testing the Refresh Counter, but it may be used for lots of other purposes too. The benefit is to not use external multiplexers, which may be timing critical too, and only use the Build In Refresh Counter. It is not possible to load the refresh counter with a value, and it is only possible to use for serial sampling.

The CAS before RAS Refresh Counter Test Cycle (from HYB514256 datasheet):
Read Cycle

Write Cycle

It is possible to use R/W cycles too, or page mode. (Page mode in the Counter Refresh Test Cycle is not documented in HYB51426 datasheet).

Typical Application:
DRAM Aplication

The counter, bit Q2 to Q10 counts to 512-1 = 511. Then it interfere with the internal refresh counter, and every time the external counter resets, will internal counter be incremented with 1 compared to last cycle.

The total samples is 511 * 512 = 261632 samples.

Since the DRAM stores the CAS address will the counter not need to be synchronous, but a higher speed may be possible if using a synchronous counter (or an LFSR, Linear Feedback Shift Register).

The counter bit Q2 to Q10 counts to 511 and Q0 to Q10 counts to 511*4 = 2044.

It is possible to obtain up to 4.5 MHz. The timing depends on delay and the possible delay in the asynchronous counter.

Not all 256K modules has full refresh counter. Typical 262144 x 4 organized DRAM's has 512 refresh cycles, while 262144 x 1 organized DRAM's has 256 refreshes only. 256K modules may contain 9x 262144 x 1 DRAM's with only 256 refresh cycles. Then only 511*256 = 130816 samples is stored. Also 256K x 1 and 256K x 4 mixed modules exist.

High Speed Fast Page Mode Sampling.

A significant higher speed is possible by using Fast Page Mode. Two memory modules is coupled parrallel, and when first module refresh is next module reading / writing in page mode. It is possible to get about 25 MHz with 70ns DRAM module, but a more sofisticated timing is required. An extra module allows 50MHz. (One inverted CAS).

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© 1997, and 1998, Jens Dyekjær Madsen.
E-Mail address: Jens.Madsen@post3.tele.dk

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